Flip flop
Table of Contents
Flip flop –
“A digital computer needs devices which can store information.”
A flip flop is a binary storage device , it can store binary bit either 0 or 1.
It has two stable States : high and low I.e. 1 , 0 .
Or
A basic sequential logic circuit is a flip flop has bistable state or two stable state , first is “0” and second is “1” .
Type of flip flops –
1. R-S flip flop
2. D – flip flop
3. J – k flip flops
4. Master slave J-K flip flop.
Characteristics –
flip flop is a bistable device, it has only two States 0 and 1 .
Flip flop has two outputs , one output is complement of other.
R-S flip flop –
A flip flop is a device with two stable state. It is reset and second is set.
The S-R latch is the simplest flip flop.
It is also called S-R (R-S) flip flop.
In this circuit one of the transistors it Saturated and the other is cut off.
We discuss two type of R-s flip flop :
1 Transistor latch
2. diode latch
Transistor latch using :
There are two control input S and R
1. In first case when S = 0 , R = 0 . Then transistor T1 not working because of forward bias now T2 base find R = 0 and from Q point as 5v voltage.
It T2 is saturated the T2 connected to ground and Q connect T2 Then point Q = 0 .
2. Second case R = 0 , S = 1 .
S = 1 connect to transistor T1 base point T1 saturated and T1 connect to ground so Q = 0.
Now Q = 0 , R = 0 both value to comes T2 each transistor than T2 not working but transistor T1 connect to Q , so Q = 1
3. Third case R = 1 , s = 0 for value of R = 1 T2 transistor then T2 not working ,
but transistor T1 connect to Q so We find transistor Q = 1
Third case R = 1 ,S = 0 for value of R , T2 transistor saturated and Q connect to ground Q = 0
Then Q = 0 , s = 0 both values comes for T1 transistor but T1 not saturated Q = 0.
4. Fourth case R = 1 , s = 1 . This is called race condition .
| R | S | Q | Comment |
| 0 | 0 | NC | NO CHANGE |
| 0 | 1 | 1 | SET (0) |
| 1 | 0 | 0 | RESET (0) |
| 1 | 1 | NA | NOT ALLOWED |
Timing diagram –
Diode latch R-S flip flop –
There are two types of diode latch flip flops –
1. NOR latches
2. NAND latches
NOR latches –
R-S (S-R) flip flop can be constructed with the help of 2 NOR gates which are available as ICs .
Working-
1. Let Q = 0 and Q = 1 in ( initial value) when R=0 and S = 0.
Now the inputs to hence output q = 0
similarly input to the NOR Gate B are S = 0 and q = 0 , then output Q = 1.
Hence no change in the state of ff.
2. when R = 0 , S = 1.
Now the input the NOR gate B are S=0 and Q = 1 the output Q should be 0.
Q = 0
similarly now the inputs to the NOR Gate A are R = 0 and Q = 0 hence it is output Q = 1
hence the result of the FF set .
3. when R=1 , S = 0
Now the input the NOR gate A are R = 1 and Q = 0 then the output Q should be 0 .
Q= 0
similarly now the inputs to the NOR gate B are s = 0 , Q = 0 then the output Q=1
This condition are reset.
4. When both S and R. R = 0 , S= 1
then both the output Q and Q will be forced to be in 0 state.
But Q = 0 and Q = 0 is meaningless
condition are not allowed
Truth table –
| R | S | Q | Q | Comment |
| 0 | 0 | 0 | 1 | NO CHANGE |
| 0 | 1 | 1 | 0 | SET |
| 1 | 0 | 0 | 1 | RESET |
| 1 | 1 | 1 | 0 | NOT ALLOWED |
NAND latches –
1. initially let Q = 0 , Q = 1 suppose R = 1 and S = 1 , Then input to the NAND Gate A are S = 1 , Q = 1 , so that the output Q = should be in o state.
Q = 0
similarly the NAND Gate B are R = 1 , Q = 0
Then the outputs becomes Q should be 1 .
Q = 1
The condition is no change.
2. when R = 1 , S = 0.
when the inputs S = 0 and Q = 1 with the NAND Gate A form the output becomes Q should be 0.
Q = 0
similarly the NAND gate B are R = 1 and Q = 0 .
Then the output become Q should be 0.
Q = 1.
3. When S = 1 and R = 0.
Now the gate III condition just opposite. Then it is obvious that the flip flop resets.
I.e. Q becomes 0.
4. when R = 0 , S = 0 .
Then the don’t case condition lead to the result that Q = 1 , Q = 1 , but this is meaningless.
The condition is not allowed.
Truth table –
| R | S | Q | Q | COMMENT |
| 1 | 1 | 0 | 1 | NO CHANGE |
| 1 | 0 | 1 | 0 | SET |
| 0 | 1 | 0 | 1 | RESET |
| 0 | 0 | 1 | 1 | NOT ALLOWED |
Timing diagram –
Clocked flip-flop –
“This could be achieved with a modified version of the flip flop called as a clocked RS FF.”
It is very useful to add clock to SR flip flop to shown this figure.
Symbol –
Circuit diagram –
Action Of Clocked R-S Flip Flop-
1. When the clock input (CK) is low condition both the AND Gates are disabled.
Thus their output remains low (0). This makes S1 = 0 and R1 = 0 the state of the FF will not change .
2.When CLK = 1 , then the AND GATES are enabled and the S , R inputs are able to reach at the inputs of the RS FF .
Depending on the states of R and S inputs the flip flops can SET RESET .
All possible states of R and S along with the corresponding state of the output.
Working –
Case I When CLK = 0
1. S = 0 , CLK = 0 , Then S1 = 1 similarly R = 1 , CLK = 0 , R1 = 1 in NAND Gate.
S1 ,R1 NC condition.
2. S = 0 , CLK = 0 then S = 1
And R = 1 , CLK = 0 , Then R1 = 1 NC condition
3. S = 1 , CLK = 0 Then S1 = 1
R = 0 , CLK = 0 Then R1 = 1
4. S = 1 , R = 1 , then NC change.
CASE II . When CLK = 1
1. s = 0 , CLK = 1 Then S1 = 1
R = 1, CLK = 1 Then R1 = 0 and
We know S1 = 1 , R1 = 0 is called reset condition Q = 0
2. S = 1, CLK = 1 Then S1 =0
R = 0 , CLK = 1 Then R1 = 1
and we know S1 = 0 , R1 = 1 is called set condition Q = 1
3. S = 0 , CLK = 1 then S1 = 1
R = 0 , CLK = 1 then R1 = 1 and
S1 and R1 = 1 Then Q = no change.
Truth Table –
| CLK | S | R | S1 | R1 | Q |
| 0 | 0 | 0 | 1 | 1 | NC |
| 0 | 0 | 1 | 1 | 1 | NC |
| 0 | 1 | 0 | 1 | 1 | NC |
| 0 | 1 | 1 | 1 | 1 | NC |
| 1 | 0 | 1 | 1 | 0 | 0 (RESET) |
| 1 | 1 | 0 | 0 | 1 | 1 (SET) |
| 1 | 0 | 0 | 1 | 1 | NC |
| 1 | 1 | 1 | 0 | 0 | NOT ALLOWED |
Timing diagram –
Disadvantage –
1. race condition.
2. level locking (means only one Level work (high).
D flip flop –
“Clocked RS flip flop can be modified to a better version called as D-type flip-flop.”
This flip flop possesses only one data input. The D flip flop is widely used , it is also know as a data or delay flip flop.
Symbol –
Circuit Diagram –
Working –
CASE I .
When D = 1 then S = 1 and R = 0 hence as clock goes high , the flip-flop will be Set or Q will become 1
Q = 1 .
CASE II.
If D = 0 then S = 0 and R = 1 Hence as the clock goes high the flip-flop will RESET
Q = 0
Edge Triggered Flip Flop –
The clock input pulses and corresponding output at the differentiating circuit. This output consists of positive and negative going spikes.
There are two types –
1. Positive edge triggered FF –
The flip-flop responds for 0 to 1 change of the clock pulse such a flip flop is called as a positive edge triggered flip flop.
2. Negative Edge Triggered Flip Flop –
A circuit which respond to 0 to 1 change of the clock pulse or at the fulling edge is called as a negative edge triggered flip flop.
Symbol & Circuit Diagram –
CASE I . When CLK = 0 then each value of D use find the output no change.
CASE II. When CLK = 1
1. When CLK = 1 Then D value do not. Then output find NC condition.
2. IF CLK is falling edge output remains find NC condition.
3. If CLK is rising edge then D = 1 then find output Q = 1 .
4. If CLK is rising edge and D = 0, then find output Q = 0.
Truth Table –
| CLK | D | Q |
| 0 | X | NC |
| 1 | X | NC |
| DOWN | X | NC |
| UP | 0 | 0 |
| UP | 1 | 1 |
Disadvantage –
In this output change only on the rising or falling edge of CLK .
Preset And Clear –
It should be clear that the output of a flip flop changes whenever a clock pulse is applied.
These leads which help to set or clear (reset) the flip-flop are independent of clock . This will be clear form the discussion to follow.
Preset –
Preset is called “direct set” means unclocked.
Clear –
Clear is called “direct reset“.
Working –
1. when preset = clear = 0 then gate P and Q both don’t case their second output is not allowed Q = * .
2. when preset = 0 , clear = 1 then R = 0 , but Q gate depend upon their second input in the NAND Gate latch , don’t care Q = 1.
3. when preset = 1 clear = 0 then S = 0 , so don’t care Q = 1 and similarly Q = 1 (Reset ).
4. when preset = 1 = clear then if CLK = 0 for P gate input are 1 there R = 1 similarly S = 1 then output NC condition.
5.Preset = clear = 1 then CLK = 1
A’ = 0 , Preset = 1 then R = 0
B’ = 0 , clear = 1 then S = 0
6. Preset = clear = 1 then CLK = low
A’ = x then R = 1
B’ = x then S = 1
NC condition.
7. Preset = 1 = clear then CLK = high
D= 0 , CLK = High , A’ = 1 , Preset = 1 , R = 1
And D’ = 1 ,CLK = high, B’ = 0 , clear = 1 , S =0.
8. Preset = 1 = clear then CLK = high
D = 1 , CLK = high , A’ = 0, Preset = 0, R= 0
D’ = 0 , CLK = high , B’ = 1, clear = 1, S = 1
1 set.
Truth table –
| Preset | clear | CLK | D | Q |
| 0 | 0 | x | x | * |
| 0 | 1 | x | x | 1 |
| 1 | 0 | x | x | 0 |
| 1 | 1 | 0 | x | NC |
| 1 | 1 | 1 | x | NC |
| 1 | 1 | down | x | NC |
| 1 | 1 | up | 0 | 0 |
| 1 | 1 | up | 1 | 1 |
Timing Diagram –
Propagation Delay-
Propagation delay is the amount of time taken for the output of a gate.
o
A flip flop to change State after the input changes states. Output changing 0 to 1 and 1 to 0 .
Setup Time –
The setup time t is the minimum time for which the data bit must be present before the clock pulse arrives.
Hold Time –
Hold time is the minimum time for which the data must remain present after the edge of the clock pulse.
J-K flip flop –
“A J-K flip flop is a modification of the R-S flip flop in that uncertain state of the RS type is defined in the JK type.”
Or
“J-K flip flop is an essential building block of sequential circuits such as counters and shift registers.”
The data at the J and K inputs of the JK flip flop controls (set and reset) output.
Symbol & Circuit diagram –
Working –
1. When J = K= 0 (inactive State)
Both J and K = 0 clock pulse has no effect O/P.
Then R = 1 , S =1 then o/p is same NC condition.
2. When J = 0 , K = 1 (reset stage)
When J = 0 the o/p of AND GATE corresponding to J becomes 0.
example – R = 1 , S = 0 then the o/p Q is reset condition means Q = 0.
3. Set state ( J = 1 , K = 0 )
This case Q = 1, the AND gate responding to k becomes 0 ,
example R = 0 and S = 1 Therefore Q = 0 and Q = 1 it is called set condition.
Q = 1
4. Toggle stage –
J = 1 , K = 1
In this case R = 0 , S = 0 , toggle Mode.
Truth Table –
| CLK | J | K | Q |
| 0 | x | x | NC |
| 1 | x | x | NC |
| Down | x | x | NC |
| X | 0 | 0 | NC |
| Up | 0 | 1 | RESET (0) |
| Up | 1 | 0 | SET (1) |
| Up | 1 | 1 | Toggle (0) |
Timing Diagram –
In RS flip flop S = R = 1 gives unpredictable state of the output. In a JK flip flop J = k = 1 is permissible. In this condition the state output is changed , complement of the previous state is available .
If in the previous stage Q is 0 it becomes 1 and vice versa :
If a JK flip flop is level triggered ,the output is not stable with J = K = 1 so long as the clock is high . The output goes on changing its State to avoid such oscillations an R-C circuit is incorporated in the clock input circuit to make a J-K flip flop edge triggered , gives stable o/p.
Master slave JK flip flop –
“A JK master slave flip flop consists of two Gates or clocked RS flip flops called as a master and a slave.”
Output of the second flip flop (slave) is (fed) back to the input of the first (master) as shown fig .
When clock is high master is active and slave is inactive.
When clock is low master inactive but slaves is active.
Symbol and Circuit diagram –
Working-
1. Set Conditions –
J = 1 , K = 1 and clock = high , if Q = 0 , Q = 1 (previous state) then master will set in R = 1, S = 0 and slave will inactive .
When clock = low
In case master inactive but slave FF active and find input R = 1, s = 0 then R’ = 0 , S’ = 1 and output Q = 1 , Q = 0 , it is called set condition .
2. Reset Conditions
J = 0 , k = 1 clock = high in preset condition Q = 1, Q = 0 of flip flop.
During the high clock signal master will reset R = 0 , S = 1 but output remains same ( in preset condition Q = 0 ,Q = 1 ) as the slave will be inactive when clock is low .
When the clock signal is low : then master will be inactive and slaves be active so flip flop remains find reset it means Q = 0 , Q = 1.
Toggle condition –
J = K =1
In this above condition Q = 0 , Q = 1 (pre) condition of flip flop.
During the high clock signal master will toggle (means R = 0 , S = 1) so R= 1 , S = 0 and output remains same (Q = 0 , Q = 1) as the slave will be inactive when clock is high.
when low clock signal arrives master will be inactive and slave will be active which toggle the flip-flop output Q = 1 , Q = 0.
Truth table –
| CLK | J | K | Q | Q | COMMENT |
| 1 | 1 | 0 | 1 | 0 | SET |
| 1 | 0 | 1 | 0 | 1 | RESET |
| 1 | 1 | 1 | 1 | 0 | TOGGLE |
Master Slave Flip Flop With Preset And Clear –
Truth Table-
| PRESET | CLEAR | CLK | J | K | Q |
| 0 | 0 | x | x | x | * |
| 0 | 1 | x | x | x | 1 |
| 1 | 0 | x | x | x | 0 |
| 1 | 1 | x | 0 | 0 | NC |
| 1 | 1 | up to down | 0 | 1 | 0 |
| 1 | 1 | up to down | 1 | 0 | 1 |
| 1 | 1 | up to down | 1 | 1 | Toggle
|
You should take part in a contest for one of the best blogs on the web. I will recommend this site!
Hello, Neat post. There’s a problem together with your site in internet explorer, might check this… IE nonetheless is the market chief and a huge part of other folks will pass over your magnificent writing due to this problem.
You made some first rate factors there. I regarded on the internet for the problem and found most people will go along with together with your website.
Write more, thats all I have to say. Literally, it seems as though you relied on the video to make your point. You clearly know what youre talking about, why waste your intelligence on just posting videos to your site when you could be giving us something enlightening to read?
Today, I went to the beach with my children. I found a sea shell and gave it to my 4 year old daughter and said “You can hear the ocean if you put this to your ear.” She put the shell to her ear and screamed. There was a hermit crab inside and it pinched her ear. She never wants to go back! LoL I know this is entirely off topic but I had to tell someone!
I was looking at some of your content on this internet site and I conceive this site is very instructive! Keep putting up.
I like studying and I believe this website got some truly utilitarian stuff on it! .
I’d constantly want to be update on new blog posts on this website , saved to favorites! .
Hey there! This is my first comment here so I just wanted to give a quick shout out and say I really enjoy reading through your blog posts. Can you recommend any other blogs/websites/forums that go over the same subjects? Appreciate it!
Way cool, some valid points! I appreciate you making this article available, the rest of the site is also high quality. Have a fun.